The present invention relates to electronic read/write memories, and, more particularly to such memories that can operate as first-in/first-out (FIFO) shift registers.
Using the common vertical metaphor, a FIFO shift register includes a control section which directs input data to a data "top" cell. The "top" cell is more precisely characterized as the bottommost cell which is vacant, that is, without valid data; all cells below this "topmost" cell are occupied with data. In effect, such a FIFO is a variable length shift register, the length of which is always the same as the data stored within. Thus, when data is "pulled" from the FIFO, each data bit shifts down one cell, as does the top cell position.
FIFO shift registers are commonly used to buffer and interface between two systems with incommensurate timing characteristics. They are often included in devices such as tape recorders, electronic typewriters and word processors.
For example, FIFO shift registers can be used to interface the analog and digital subsystems of the read circuitry in a high-performance tape drive system. In such a system, data is typically recorded as on parallel tracks of flux levels on a magnetic tape. The tape is passed over a read head which converts the magnetic flux levels of each track into analog electrical signals. These analog electrical signals are then digitized and fed into read/format circuitry for decoding.
While the timing within the read/format circuitry can be precisely synchronized according to a system clock, it is not a trivial matter to coordinate this digital circuitry with the incoming analog signal tracks, and to coordinate the individual signal tracks with each other. The timing of the data in the form of flux reversals on the tape is subject to the vagaries of mechanical speed fluctuations, tape or head misalignment, and tape deformation. Thus, the individual data tracks can be skewed with respect to each other and generally bear no intrinsic relation to the synchronization governing the read/format circuitry.
In order to interface the analog and digital circuits, each track can be processed by a phase locked loop, a FIFO shift register and de-skew circuitry. Each phase locked loop samples and assigns digital values to segments of the incoming analog signal. The phase locked loop also determines which samples are valid, i.e. represent a single bit of data, rather than a transition between two bits. In accordance with such determination, the phase locked loop determines when "push" commands are issued for the FIFO to accept a data input. The de-skew circuitry looks for certain timing marks written into the data tracks and can issue or withhold "pull" commands which withdraw data from the FIFO and cause the contents to shift down. Thus, the FIFO shift registers serve to buffer the interface between the analog and digital subsystems of the read circuitry.
However, available FIFO shift register designs can constrain system performance due to cost, reliability and speed limitations. Most of these limitations are related to the difficulty of implementing current FIFO designs in very large scale integrated (VLSI) circuits. VLSI technology provides for very cost effective manufacture of complex circuits. This translates into significant savings with respect to simple circuits that can be integrated into a larger system implemented on a VLSI device. Likewise, a circuit included in a VLSI device can obtain speed advantages due to the short electrical paths involved and reliability advantages due to the minimization of separate interfacing manufacturing steps.
However, the reliability of VLSI devices is dependent on the manufacturer's ability to discard defective devices. This, in turn, requires that the designs implemented in VLSI be readily testable. Testability is in large part dependent on the design being entirely synchronous.
Thus, intelligent circuit design involves integrating circuits synchronized to a common clock on a monolithic device, such as a read/format chip, while leaving asynchronous components off. Thus, it can be said that a synchronization boundary limits which devices can take advantage of VLSI. Available FIFO shift register designs are asynchronous and thus must lie outside a synchronization boundary. Likewise, components separated from a synchronous subsystem by such a FIFO shift register are outside the synchronization boundary so that it is difficult to obtain advantages by integrating them into a main system chip.
Thus, current FIFO shift register designs cannot reliably take advantage of VLSI technology; this limitation extends to other components, e.g., those upstream from a FIFO shift register in tape recorder read circuitry. A related disadvantage is that it is difficult to coordinate the operation of FIFOs arranged in parallel, as is often the case in tape drive read circuitry. In addition, FIFO shift registers can delay system operation during the time it takes for a data bit to "bubble-through" to the top cell. Thus, there is a need for a FIFO shift register, which provides for higher speed operation, integration into VLSI devices, and coordination with other FIFO shift registers arranged in parallel.